VHDL语言设计自整定模糊PID

问题描述：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity discrete is
port(clk:in STD_LOGIC;
e,ec:in STD_LOGIC_VECTOR(7 downto 0);
eo,co:in STD_LOGIC
elunyu,eclunyu:out STD_LOGIC_VECTOR(3 downto 0));
end discrete;
architecture discrete of discrete is
begin
process(clk)
begin
if clk'event and clk='1' then
if eo='0' then
if e<"00000001" then
elunyu<="0000";
elsif "00000001"<=e and e<"00000011" then
elunyu<="0001";
elsif "00000011"<=e and e<"00000100" then
elunyu<="0010";
elsif "00000100"<=e and e<"00000110" then
elunyu<="0011";
elsif "00000110"<=e and e<"00001000" then
elunyu<="0100";
elsif "00001000"<=e and e<="00001001" then
elunyu<="0101";
elsif "00001001"<=e and e<="11111111" then
elunyu<="0110";
end if;
elsif eo='1' then
if e<"00000001" then
elunyu<="0000";
elsif "00000001"<=e and e<"00000011" then
elunyu<="1001";
elsif "00000011"<=e and e<"00000100" then
elunyu<="1010";
elsif "00000100"<=e and e<"00000110" then
elunyu<="1011";
elsif "00000110"<=e and e<"00001000" then
elunyu<="1100";
elsif "00001000"<=e and e<"00001001" then
elunyu<="1101";
elsif "00001001"<=e and e<"11111111" then
elunyu<="1110";
end if;
end if;
end if;
end process;
end architecture discrete;

这是量化；

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rom is
port(elunyu,eclunyu:in STD_LOGIC_VECTOR(3 downto 0);
kp,ki:out STD_LOGIC_VECTOR(7 downto 0));
end rom;
architecture rom of rom is
begin
process(elunyu,eclunyu)
variable addr:std_logic_vector(7 downto 0);
begin
addr:=elunyu&eclunyu;
case addr is
when "11101110"=>
kp<="10010011";
ki<="00111110";
when "11101101"=>
kp<="10000101";
ki<="01001001";

when others=>
kp<="00000000";
ki<="00000000";
end case;
end process;
end architecture rom;
这是rom单元
在线等待！！
谢谢@~~

问题解答：

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